1. FIELD OF THE INVENTION
The present invention relates to the field of semiconductor integrated circuit manufacturing, and, more specifically, to a method of forming a planar and reliable trench isolation region in a semiconductor substrate.
2. DESCRIPTION OF RELEVANT ART
Deep and narrow trench isolation structures are presently used in integrated circuit manufacturing. Deep trench isolation structures can be used to isolate n-channel and p-channel devices in CMOS circuits. Additionally, trench isolation structures can be used to isolate transistors of bipolar circuits. Deep trench isolation structures are useful because they provide isolation while only using limited substrate area. Small dimensioned isolation regions will be needed in future ultra large scale integrated (ULSI) circuits which will require high packing density of electronic devices. Despite its many advantages, deep trench isolation technology has been hindered by fabrication complexity and reliability considerations.
For example, FIGS. 1a-1f detail a prior art method of forming a deep trench isolation structure in a bipolar circuit. First, as shown in FIG. 1a, well-known process steps are used to etch a deep trench 102 into a substrate 100 for bipolar transistors. Next, as shown in FIG. 1b, a trench oxide 106 is grown on the surface of substrate 100 and in trench 102 (i.e. on the sidewalls and on the bottom of trench 102). Next, an amorphous silicon or polysilicon layer 108 is formed on the trench oxide layer. The polysilicon layer is deposited until it completely refills trench 102. Next, as shown in FIG. 1c, polysilicon layer 108 on the surface of substrate 100 is etched back. The polysilicon etch-back process slightly recesses polysilicon refill 108 into trench 102. Next, trench oxide 106 on substrate 100 is removed. Unfortunately, the trench oxide strip step removes some of the trench oxide 106 along the sidewalls of trench 102, thereby forming gaps 110 between substrate 100 and polysilicon refill 108. Trench oxide gaps 110 cause downstream process problems.
Typically a thin pad-oxide layer 112 and a silicon nitride layer 114 are generally formed next on substrate 100 as shown in FIG. 1d. It is to be appreciated that pad-oxide 112 and silicon nitride 114 form in trench oxide gaps 110. Next, pad oxide 112 and silicon nitride 114 are patterned to open a window for a subsequent field oxidation. Unfortunately, as shown in FIG. 1e, after silicon nitride layer 114 and pad oxide layer 112 are patterned, a nitride residue 116 remains in gaps 110 which were formed in trench oxide 106 during the trench oxide strip step. It is to be noted that nitride residue 116 prevents oxidation of trench sidewalls wherever it is present.
As a result, as shown in FIG. 1e, a non-planar field oxide layer 118 is grown. Thin deep depressions 120 are created in field oxide 118 due to the retarded growth of the oxide layer at nitride residue locations 116. Depressions 120 can cause reliability problems in later processing steps. For example, polysilicon used to form collectors in bipolar circuits, or gate electrodes in CMOS circuits, can become trapped in depression 120 and cause shorts between adjacent lines. Another problem with the prior art process of forming a trench isolation structure is that the field oxidation layer 118 is grown above substrate 100 creating a non planar surface topography. That is, field oxide 118 and the top surface of substrate 100 are non planar. Such a non-planar surface topography adversely affects subsequent processing steps and is especially troublesome for photolithography definition of submicron lines used in the manufacture of ULSI circuits.
Thus, what is desired is a method of forming a reliable, deep trench isolation structure which has a planar surface topography and which can be used in the latest high density integrated circuits.